1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a liquid crystal display device and a driving method thereof that is adaptive for restraining a generation of a transient current.
2. Discussion of the Related Art
Generally, a liquid crystal display device has an inherent resolution corresponding to the number of integrated pixels, and has a higher resolution as its dimension becomes larger. In order to display a high quality of picture, makers of the liquid crystal display device increase a pixel integration ratio within a liquid crystal panel between liquid crystal display devices with same dimension to differentiate the resolution.
In the liquid crystal display device, a data clock DCLK according to the XGA class data is 65 MHz on the basis of a refresh rate of 60 Hz. More specifically, in a system including a video card, a frequency of the data clock DCLK transferred to the liquid crystal display device is 65 MHz at a XGA resolution; 108 MHz at a SXGA resolution; and 160 MHz at a UXGA resolution.
In the liquid crystal display (LCD) as mentioned above, a frequency of an accepted input data clock of driver integrated circuits for displaying a data on a liquid crystal display panel is about 45 to 60 MHz. Accordingly, the recent liquid crystal display device divides input and output data in parallel so as to reduce a high data clock frequency and transfers the data simultaneously over a plurality of transmission lines, thereby reducing driving frequencies of the driver integrated circuits.
FIG. 1 is a block diagram showing a configuration of the conventional LCD, which illustrates a LCD having a XGA class resolution. In recent, in order to reduce a frequency of a driving clock in the LCD, a data for two pixels divided into odd and even pixel data is inputted, via an interface, from the system. Thus, a frequency of the data clock DCLK is 35.5 MHz lower than 65 MHz which is a data clock frequency of an original image signal.
Referring to FIG. 1, a timing controller 10 receives odd and even data and a data clock from an interface (not shown). The timing controller 10 is synchronized with the data clock to supply a data driving circuit 20 including n data driver IC's D1 to Dn with the odd and even data. Then, the data driving circuit 20 supplies a liquid crystal display panel 30 with the odd and even data. At this time, a gate driving circuit 40 including m gate driver IC's G1 to Gm is synchronized with the odd and even data so that the liquid crystal display panel 30 may display a picture, thereby applying a pulse signal to the liquid crystal display panel 30. The data driver IC's D1 to Dn receives a source sampling signal from the timing controller 10 to latch a data.
FIG. 2 is a timing chart showing a frequency-division concept of a data clock (DCLK) frequency. Referring to FIG. 2, an original data (b) for one pixel is outputted in synchronization with a data clock DCLK1 (a). Then, the system or the LCD latches the data (b) to synchronize an odd data (d) and even data (e) with twice-frequency-divided data clock DCLK (c) and output the same simultaneously. Such a driving method is referred to as “two-port port driving method” or “six-bus driving method” because the data (d) and (e) for two pixels are simultaneously outputted, which has been disclosed in Korea Patent Application No. 95-19513 filed on Jul. 4, 1995 by the same applicant.
However, the above-mentioned conventional LCD and driving method thereof reduces a driving frequency in the LCD, but increases a data amount outputted simultaneously according to an increase in a data output. For instance, in the case of a two-port driving method in the LCD using a 8-bit data, a data is simultaneously outputted, via 48 bit lines (i.e., 48 bit line=2(port)×3(R,G,B)×8(bit)), from the timing controller 10. At this time, a transient current is generated within the timing controller 10 in a conversion process between data (high/low).
Recently, a high-resolution LCD capable of a high-resolution picture in a same size of LCD has been required to display a high quality picture. For instance, a data clock frequency in a high-resolution UXGA system is about 160 MHz. An apparatus and method in FIG. 1 according to the conventional “two-port driving method” for reducing the data clock frequency is capable of reducing a data clock into about 80 MHz. Since the above-mentioned data clock is higher than an accepted input value in the general diver IC 's, however, a frequency reduction according to a high resolution has been more required. Accordingly, another conventional apparatus and method latches a data inputted with being divided into odd and even data one line by one line using a line memory and outputs 4 pixel data simultaneously according to a division of the panel area. Such a driving method may be referred to as “four-port driving method.
FIG. 3 is an operational timing chart according to the above-mentioned conventional four-port data transmission method. In FIG. 3, as an example, n driver IC 's connected to the liquid crystal display panel 30 are two-division driven into left and right groups as shown in FIG. 2. More specifically, data data1 to data1024 for one horizontal line inputted as shown in (b) and (c) in FIG. 3 are latched, and 4 pixel data are simultaneously outputted as shown in (e), (f), (g) and (h) in FIG. 3 upon inputting of the next horizontal line data. Accordingly, an input data clock (a) has a frequency reduced to ½ like a two frequency-divided source sampling clock SSC (d).
Assuming that an LCD according to the above-mentioned driving method uses a 8-bit data as an example, an output data line of the timing controller 10 becomes 4×3(R,G,B)×8(bit)=96 bit line. Thus, when the nth four data are converted and outputted to the (n+1)th four data, a transient current is generated within the timing controller 10. More specifically, when a data conversion of Low/High or High/Low is made, or when a plurality of data conversion of Low/High is made, a transient current flows in the timing controller 10.
Such a transient current shortens a life of the LCD and makes an adverse effect to devices such as a DC to DC converter (not shown) for a current supply, and generates an analog power noise, etc. Furthermore, the conventional LCD additionally requires a capacitor for eliminating the transient current to cause a complex configuration and a cost rise.